1. Field of the Invention
The invention relates to a circuit arrangement for converting a digital data signal having a first clock frequency into a signal having a second clock frequency, comprising an interpolator/decimator which includes a series of successively connected input registers for the data signal, each register comprising a clock input for a register clock signal, a data input for the data signal, and a data output which is coupled to an input of arithmetic circuits for calculating a linear combination of output signals. Using the arithmetic circuits, the output signals of the registers can be multiplied by filter coefficients and added subsequently.
The invention also relates to an image display device or television apparatus comprising an input for a digital input signal, which image display apparatus comprises such a circuit arrangement for converting the digital input signal into a digital signal of a second clock frequency as well as means for generating images on a display screen on the basis of a digital signal of the second clock frequency.
2. Description of the Related Art
A circuit arrangement of this kind is known, for example from European Patent Application 0 336 669. Like many other such known arrangements, however, the described circuit arrangement operates on the basis of a given, fixed rational numerical ratio of the first and the second clock frequency. Thus, the range of application of these circuit arrangements is substantially limited in that the frequency ratio of the two clock signals must have a known, fixed value. The reason why this limitation is to be imposed on the known circuit arrangement is that all circuit arrangements of this kind necessarily operate with registers in which the data is buffered. Part of these registers must be clocked at the first frequency and another part is clocked at the second frequency. A problem is then encountered in that such registers can be realized only so that the data present at the input of a register for transfer in said register may not change during a given time interval. This is the time interval preceding and succeeding the clock pulse edge whereby the data is to be transferred into the register. Moreover, after the transfer of the data into the register, the data appears at the output only after a time delay and does not become valid until after said period of time has elapsed. These periods of time are customarily designated as "data set-up time" and "data hold time". Because of these periods during which the input data may not be modified or the output data is not yet valid, respectively, successively connected registers clocked at different clock frequencies give rise to the problem that when the edges of the clock signals overlap, the output data of the first register will change of -at a moment- when the input signals of the second register may not be modified. The data written into the second register is then undefined and represents a signal disturbance.
European Patent Application 0 227 172 discloses a coefficient generator comprising a closed phase control loop for a filter which operates with a non-rational ratio of the input and output frequencies. The cited Application essentially relates to the problem of generating the filter coefficients and only marinally deals with the arrangement for converting the clock frequency. Again a fixed ratio exists between the two clock signals; however, according to the teaching of this application they may also exhibit a non-rational ratio. For compensation of the two clock frequencies a buffer memory is connected to the output of the circuit arrangement.